1. Field of the Invention
The present invention relates to a leveling apparatus and an atomic force microscope including the same, and more particularly, to a leveling apparatus that levels a leveling object with a surface of a substrate by directly measuring a force applied to the leveling object, and an atomic force microscope including the leveling apparatus.
2. Description of the Related Art
Lithography is used in various fields of science and technology including production of an integrated circuit, a storage, a video screen, an MEMS (microelectromechanical systems), a down-sized sensor, a microfluidic system, a biochip, a photonic bandgap structure, and a diffractive optical element, and recently, dip-pen nanolithography and polymer pen lithography have been developed.
Dip-pen nanolithography (DPN) that enables the tip of a cantilever of an AFM (Atomic Force Microscope) to function as a pen, covers the tip with a chemical compound or a mixture that function as ink, and then brings the tip in contact with a substrate, has been developed by the research team of Chad Mirkin at Northwestern University.
Thereafter, F. Huo et al. at Northwestern University have developed PPL (Polymer Pen Lithography) that allows for printing points of 90 nm to hundreds of micrometers (μm) quickly at a low cost, using a PPA (Polymer Pen Array) manufactured by the conventional photolithography and chemical wet etching in the related art.
The DPN and PPL, direct-write nanolithographic approaches, are expected to high throughput, multiplexing, and productivity and can be used for various purposes, so recently they have been actively studied.
In the DPN and the PPL, an array with tips or polymer pens arranged on a one-dimensional line or a two-dimensional plane is used in most cases, but the more the number of the tips or the polymer pens in the array increases or the more the array is complicated, the more it is difficult to bring the array horizontally in contact with the surface of a substrate. If the array is not horizontally on the surface of a substrate, one tip or one polymer pen is brought first in contact with the surface of the substrate before another tip or polymer pen is brought in contact with the surface of the substrate, such that there are left tips or polymer pens that were not brought in contact with the surface.
When there are tips or polymer pens that were not brought in contact with the surface of the substrate, desired lithography cannot be made on the substrate and the tips or polymer pens brought first in contact with the surface are easy to be damaged by excessive pressure. Accordingly, the array requires high degree of flatness and it is important to level the array arranged with tips or polymer pens with the surface of the substrate.
However, since the array arranged with tips or polymer pens is very small in area, it is not easy to check leveling of the array with the surface of the substrate.
Studies of leveling an array arranged with tips or polymer pens with the surface of the substrate have been conducted and there has been disclosed a method that levels an array with the surface of the substrate at the angle where the largest force is applied, by measuring changes in force with changes in the angle of the array, using an apparatus that places a substrate to come in contact with an array on a balance and measures the force applied to the surface of the substrate at the moment of contacting (Patent Document 1).
FIG. 1 is a graph illustrating distribution of force measured by the apparatus disclosed in Patent Document 1 and it can be seen from FIG. 1 that the largest force is measured at the point where an array and the surface of a substrate are leveled, by repeating measurement of the force with changes in angle θ made by the array and X axis and the angle φ made by the array and Y axis.
However, the leveling method disclosed in Patent Document 1 requires many repeat tests to achieve the graph illustrated in FIG. 1, such that there is a problem in that a lot of time is taken, the array may be damaged during tests, and the cost increases due to reduction of lifespan of the array.
(Patent Document 1)    US Patent Publication No. US2011/0165329A1